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freescale semiconductor data sheet document number: mcf5213ec rev. 3, 05/2007 ? freescale semiconductor, inc., 2007. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mcf5213 lqfp?64 10 mm x 10 mm mapbga?81 10 mm x 10 mm lqfp?100 14 mm x 14 mm qfn?64 9mmx9mm the mcf5213 is a member of the coldfire ? family of reduced instruction set computing (risc) microprocessors. this document provides an overview of the 32-bit mcf5213 microcontroller, focusing on its highly integrated and diverse feature set. this 32-bit device is based on the version 2 coldfire core operating at a frequency up to 80 mhz, offering high performance and low power consumption. on-chip memories connected tightly to the pro cessor core include up to 256 kbytes of flash memory and 32 kbytes of static random access memory (sram). on-chip modules include: ? v2 coldfire core delivering 76 mips (dhrystone 2.1) at 80 mhz running from internal flash memory with multiply accumulate (mac) unit and hardware divider ? flexcan controller area network (can) module ? three universal asynchronous/synchronous receiver/transmitters (uarts) ? inter-integrated circuit (i2c?) bus controller ? queued serial peripheral interface (qspi) module ? eight-channel 12-bit fast analog-to-digital converter (adc) ? four-channel direct memo ry access (dma) controller ? four 32-bit input capture/output compare timers with dma support (dtim) ? four-channel general-purpose timer (gpt) capable of input capture/output compare, pulse width modulation (pwm), and pulse accumulation ? eight-channel/four-channel, 8-bit/16-bit pulse width modulation timer ? two 16-bit periodic interrupt timers (pits) ? programmable software watchdog timer ? interrupt controller capable of handling 57 sources ? clock module with 8 mhz on-chip relaxation oscillator and integrated phase-locked loop (pll) ? test access/debug port (jtag, bdm) mcf5213 coldfire microcontroller supports mcf5213, mcf5212, & MCF5211
mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 2 table of contents 1 mcf5213 family configurations . . . . . . . . . . . . . . . . . . . . . . .3 1.1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 pll and clock signals . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.6 external interrupt signals . . . . . . . . . . . . . . . . . . . . . . .21 1.7 queued serial peripheral interface (qspi). . . . . . . . . .21 1.8 i 2 c i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.9 uart module signals . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.10 dma timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.11 adc signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.12 general purpose timer signals . . . . . . . . . . . . . . . . . .23 1.13 pulse width modulator signals . . . . . . . . . . . . . . . . . . .23 1.14 debug support signals . . . . . . . . . . . . . . . . . . . . . . . . .23 1.15 ezport signal descriptions . . . . . . . . . . . . . . . . . . . . . .24 1.16 power and ground pins . . . . . . . . . . . . . . . . . . . . . . . .25 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.2 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .28 2.4 flash memory characteristics . . . . . . . . . . . . . . . . . . .30 2.5 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.6 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .31 2.7 clock source electrical specifications . . . . . . . . . . . . .32 2.8 general purpose i/o timing . . . . . . . . . . . . . . . . . . . . .33 2.9 reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.10 i 2 c input/output timing specifications . . . . . . . . . . . . .35 2.11 analog-to-digital converter (adc) parameters . . . . . .36 2.12 equivalent circuit for adc inputs . . . . . . . . . . . . . . . . .37 2.13 dma timers timing specifications . . . . . . . . . . . . . . . .38 2.14 qspi electrical specifications. . . . . . . . . . . . . . . . . . . .38 2.15 jtag and boundary scan timing. . . . . . . . . . . . . . . . .39 2.16 debug ac timing specifications. . . . . . . . . . . . . . . . . .41 3 mechanical outline drawings . . . . . . . . . . . . . . . . . . . . . . . . .43 3.1 64-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . .43 3.2 64 qfn package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.3 81 mapbga package. . . . . . . . . . . . . . . . . . . . . . . . . .50 3.4 100-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . .52 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 list of figures figure 1. mcf5213 block diagram . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. 100 lqfp pin assignments . . . . . . . . . . . . . . . . . . . . 13 figure 3. 81 mapbga pin assignments . . . . . . . . . . . . . . . . . . 14 figure 4. 64 lqfp and 64 qfn pin assignments . . . . . . . . . . . 15 figure 5. gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. rsti and configuration override timing . . . . . . . . . . 34 figure 7. i 2 c input/output timings . . . . . . . . . . . . . . . . . . . . . . 36 figure 8. equivalent circuit for a/d loading. . . . . . . . . . . . . . . . 37 figure 9. qspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10.test clock input timing . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11.boundary scan (jtag) timing . . . . . . . . . . . . . . . . . 40 figure 12.test access port timing . . . . . . . . . . . . . . . . . . . . . . 40 figure 13.trst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14.real-time trace ac timing . . . . . . . . . . . . . . . . . . . . 41 figure 15.bdm serial port ac timing . . . . . . . . . . . . . . . . . . . . 42 list of tables table 1. mcf5213 family configurations . . . . . . . . . . . . . . . . . . 3 table 2. orderable part number summary. . . . . . . . . . . . . . . . 12 table 3. pin functions by primary and alternate purpose . . . . 16 table 4. reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. pll and clock signals . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. mode selection signals . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. clocking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. external interrupt signals . . . . . . . . . . . . . . . . . . . . . . 21 table 9. queued serial peripheral interface (qspi) signals. . . 21 table 10.i 2 c i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11.uart module signals . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12.dma timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13.adc signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14.gpt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15.pwm signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16.debug support signals . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17.ezport signal descriptions . . . . . . . . . . . . . . . . . . . . . 24 table 18.power and ground pins. . . . . . . . . . . . . . . . . . . . . . . . 25 table 19.absolute maximum ratings . . . . . . . . . . . . . . . . . . . . 26 table 20.current consumption in low-power mode , . . . . . . . . . 27 table 21.typical active current c onsumption specifications. . . 28 table 22.thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . 28 table 23.sgfm flash program and erase characteristics . . . . 30 table 24.sgfm flash module life char acteristics . . . . . . . . . . 30 table 25.esd protection characteristics, . . . . . . . . . . . . . . . . . 31 table 26.dc electrical specifications . . . . . . . . . . . . . . . . . . . . 31 table 27.pll electrical specifications . . . . . . . . . . . . . . . . . . . . 32 table 28.gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 29.reset and configuration override timing . . . . . . . . . . 34 table 30.i 2 c input timing specifications between i2c_scl and i2c_sda. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 31.i 2 c output timing specifications between i2c_scl and i2c_sda. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32.adc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 33.timer module ac timing specifications . . . . . . . . . . . 38 table 34.qspi modules ac timing specifications. . . . . . . . . . . 38 table 35.jtag and boundary scan timing . . . . . . . . . . . . . . . . 39 table 36.debug ac timing specification . . . . . . . . . . . . . . . . . . 41 table 37.revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 3 1 mcf5213 family configurations table 1. mcf5213 family configurations figure 1 shows a top-level block diagram of the mcf5213. package optio ns for this family are described later in this document. module 5211 5212 5213 coldfire version 2 core with mac (multiply-accumulate unit) ??? system clock 66, 80 mhz performance (dhrystone 2.1 mips) 63 up to 76 flash / static ram (sram) 128/16 kbytes 256/32 kbytes interrupt controller (intc) ??? fast analog-to-digital converter (adc) ??? flexcan 2.0b module see note 1 1 flexcan is available on the MCF5211 only in the 64 qfn package. ? ? four-channel direct-memory access (dma) ??? watchdog timer module (wdt) ??? programmable interval timer module (pit) 2 2 2 four-channel general-purpose timer 3 3 3 32-bit dma timers 4 4 4 qspi ??? uarts 3 3 3 i 2 c ??? pwm 8 8 8 general purpose i/o module (gpio) ??? chip configuration and reset controller module ??? background debug mode (bdm) ??? jtag - ieee 1149.1 test access port 2 2 the full debug/trace interface is available only on the 100-pin packages. a reduced debug interface is bonded on smaller packages. ??? package 64 lqfp 64 qfn 81 mapbga 64 lqfp 81 mapbga 81 mapbga 100 lqfp
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 4 figure 1. mcf5213 block diagram 1.1 features this document contains information on a new product under deve lopment. freescale reserves the ri ght to change or discontinue this product without notice. specifications and information herein are subject to change without notice. 1.1.1 feature overview the mcf5213 family includes the following features: arbiter interrupt controller uart 0 qspi uart 1 uart 2 i 2 c dtim 0 dtim 1 dtim 2 dtim 3 v2 coldfire cpu ifp oep mac 4 ch dma mux jtag tap to/from padi 32 kbytes sram (4k 16) 4 256 kbytes flash (32k 16) 4 ports (gpio) cim rsti rsto utxd n urxd n u r ts n dtin n /dtout n canrx jtag_en adc an[7:0] v rh v rl pll oco clkgen edge port flexcan extal xtal clkout pit0 pit1 gpt pwm to/from interrupt controller cantx u c ts n pmm v stby padi ? pin muxing ezport ezpcs clkmod0 clkmod1 qspi_clk, qspi_cs n pwm n qspi_din, qspi_dout gpt n ezpck ezpd ezpq swt
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 5 ? version 2 coldfire variable -length risc processor core ? static operation ? 32-bit address and data paths on-chip ? up to 80 mhz processor core frequency ? sixteen general-purpose, 32-bit data and address registers ? implements coldfire isa_a with extensions to support th e user stack pointer register and four new instructions for improved bit processing (isa_a+) ? multiply-accumulate (mac) unit with 32-bit accumulator to support 16 16 32 or 32 32 32 operations ? illegal instruction decode that allows for 68-kbyte emulation support ? system debug support ? real-time trace for determin ing dynamic execution path ? background debug mode (bdm) for in-circuit debugging (debug_b+) ? real-time debug support, with six hardware breakpoints (4 pc, 1 address and 1 data) c onfigurable into a 1- or 2-level trigger ? on-chip memories ? 32-kbyte dual-ported sram on cpu internal bus, supp orting core and dma access with standby power supply support ? 256 kbytes of interleaved flash memory supporting 2-1-1-1 accesses ? power management ? fully static operation with processor sleep and whole chip stop modes ? rapid response to interrupts from th e low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used ? flexcan 2.0b module ? based on and includes all existing f eatures of the freescale toucan module ? full implementation of the can protocol specification version 2.0b ? standard data and remote frames (up to 109 bits long) ? extended data and remote frames (up to 127 bits long) ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/sec ? flexible message buffers (mbs), totalling up to 16 mess age buffers of 0?8 byte data length each, configurable as rx or tx, all supporting standard and extended messages ? unused mb space can be used as general purpose ram space ? listen-only mode capability ? content-related addressing ? no read/write semaphores ? three programmable mask registers: global for mbs 0-13, special for mb14, and special for mb15 ? programmable transmit-first scheme: lo west id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? three universal asynchronous/synchr onous receiver transmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic with maskable interrupts ? dma support ? data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity ? up to two stop bits in 1/16 increments
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 6 ? error-detection capabilities ? modem support includes request-to-send (rts ) and clear-to-send (cts) lines for two uarts ? transmit and receive fifo buffers ?i 2 c module ? interchip bus interface for eeproms, lcd c ontrollers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master and slave modes support multiple masters ? automatic interrupt generation with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to four chip selects available ? master mode operation only ? programmable bit rates up to half the cpu clock frequency ? up to 16 pre-programmed transfers ? fast analog-to-digital converter (adc) ? eight analog input channels ? 12-bit resolution ? minimum 1.125 s conversion time ? simultaneous sampling of two channels for motor control applications ? single-scan or continuous operation ? optional interrupts on conversion complete, zero cros sing (sign change), or under/over low/high limit ? unused analog channels can be used as digital i/o ? four 32-bit timers with dma support ? 12.5 ns resolution at 80 mhz ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input capture capability with programmable trigger edge on input pin ? output compare with programmable mode for the output pin ? free run and restart modes ? maskable interrupts on input capture or output compare ? dma trigger capability on input capture or output compare ? four-channel general purpose timer ? 16-bit architecture ? programmable prescaler ? output pulse-widths variable from microseconds to seconds ? single 16-bit input pulse accumulator ? toggle-on-overflow feature for pulse-width modulator (pwm) generation ? one dual-mode puls e accumulation channel ? pulse-width modulation timer ? operates as eight channels with 8-bit resolution or four channels with 16-bit resolution ? programmable period and duty cycle ? programmable enable/dis able for each channel ? software selectable polarity for each channel ? period and duty cycle are double buffered. change takes ef fect when the end of the current period is reached (pwm counter reaches zero) or when the channel is disabled.
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 7 ? programmable center or left aligned outputs on individual channels ? four clock sources (a, b, sa, and sb) pr ovide for a wide range of frequencies ? emergency shutdown ? two periodic interrupt timers (pits) ? 16-bit counter ? selectable as free running or count down ? software watchdog timer ? 32-bit counter ? low-power mode support ? clock generation features ? one to 48 mhz crystal, 8 mhz on-chip relaxation os cillator, or external os cillator reference options ? trimmed relaxation oscillator ? two to 10 mhz reference frequency for normal pll mode with a pre-divider programmable from 1 to 8 ? system can be clocked from pll or directly fr om crystal oscillator or relaxation oscillator ? low power modes supported ?2 n (n 0 15) low-power divider for extremely low frequency operation ? interrupt controller ? uniquely programmable vectors for all interrupt sources ? fully programmable level and priority for all peripheral interrupt sources ? seven external interrupt signals with fixed level and priority ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt source or all interrupt sources (global mask-all) ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from low-power modes ? dma controller ? four fully programmable channels ? dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 32-bit) burst transfers ? source/destination address pointers th at can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers support ed for efficient block movement ? bursting and cycle steal support ? software-programmable dma requesters for the uarts (3) and 32-bit timers (4) ? reset ? separate reset in and reset out signals ? seven sources of reset: ? power-on reset (por) ? external ?software ? watchdog ? loss of clock ? loss of lock ? low-voltage detection (lvd) ? status flag indication of source of last reset ? chip integration module (cim)
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 8 ? system configuration during reset ? selects one of six clock modes ? configures output pad drive strength ? unique part identification number and part revision number ? general purpose i/o interface ? up to 56 bits of general purpose i/o ? bit manipulation supported via set/clear functions ? programmable drive strengths ? unused peripheral pins may be used as extra gpio ? jtag support for system level board testing 1.1.2 v2 core overview the version 2 coldfire processor core is comprised of two sepa rate pipelines decoupled by an in struction buffer. the two-stage instruction fetch pipeline (ifp) is responsible for instruction- address generation and instruction fetch. the instruction buffe r is a first-in-first-out (fifo) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (oep ). the oep includes two pipeline stages. the first stage decodes instructions and selects opera nds (dsoc); the second stage (agex) performs instruction ex ecution and calculates operand ef fective addresses, if needed. the v2 core implements the coldfire instruction set architectur e revision a+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. additionally, the mcf5213 core includes the multiply-accumulate (mac) unit for improved signal processing capabilities. the mac implements a three-stage arithmetic pipeline, optimized for 16 16 bit operations, with support for one 32-bit accumula tor. supported opera nds include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types . the mac provides support for execution of dsp operations within the context of a single processo r at a minimal hardware cost. 1.1.3 integrated debug module the coldfire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. through a standard debug interface, access to debug information and real-time tracing capability is provided on 100-lead packages. this allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. the on-chip breakpoint resources include a to tal of nine programmable 32-bit registers: an address and an address mask register , a data and a data mask register, four pc registers, and on e pc mask register. these registers can be accessed through the dedicated debug serial communication channel or from the pro cessor?s supervisor mode progr amming model. the breakpoint registers can be configured to generate triggers by combining th e address, data, and pc conditions in a variety of single- or dual-level definitions. the trigger event can be programmed to ge nerate a processor halt or initiate a debug interrupt exceptio n. the mcf5213 implements revision b+ of the coldfire debug architecture. the mcf5213?s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interr upt event. this ensures the system cont inues to operate even during debugging. to support program trace, the v2 debug mo dule provides processor status (pst[3:0]) and debug data (d data[3:0]) ports. these buses and the pstclk output provid e execution status, captured operand data, and branch target addresses defining processor activity at the cpu?s clock rate . the mcf5213 includes a new debug signal, allpst. this signal is the logical and of the processor status (pst[3:0]) signals and is useful for detecting when the processor is in a halted state (pst[3:0] = 1111 ). the full debug/trace interface is available only on the 100-pin packages . however, every product f eatures the dedicated debug serial communication cha nnel (dsi, dso, dsclk) and the allpst signal.
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 9 1.1.4 jtag the mcf5213 supports circuit board test strategies based on th e test technology committee of ieee and the joint test action group (jtag). the test logic includes a test access port (tap) co nsisting of a 16-state controller, an instruction register, an d three test registers (a 1-bit bypass register, a 256-bit boundary -scan register, and a 32-bit id register). the boundary scan r egister links the device?s pins into one shift register. test logic, impl emented using static logic design, is independent of the devic e system logic. the mcf5213 implementation can: ? perform boundary-scan operations to te st circuit board electrical continuity ? sample mcf5213 system pins during oper ation and transparently shift out the result in the boundary scan register ? bypass the mcf5213 for a given circuit board test by eff ectively reducing the boundary-scan register to a single bit ? disable the output drive to pins during circuit-board testing ? drive output pins to stable levels 1.1.5 on-chip memories 1.1.5.1 sram the dual-ported sram module pr ovides a general-purpose 32-kbyte memory bl ock that the coldfire core can access in a single cycle. the location of the memory block can be set to any 32-kbyte boundary within the 4-gbyte address space. this memory is ideal for storing critical code or data structures and for use as the sy stem stack. because the sram module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. the sram module is also accessible by the dma. the dual-ported nature of th e sram makes it ideal for implementing applications with double-buffer schemes, where the processor a nd a dma device operate in altern ate regions of the sram to maximize system performance. 1.1.5.2 flash memory the coldfire flash module (cfm) is a non-volatile memory (n vm) module that connects to th e processor?s high-speed local bus. the cfm is constructed with four banks of 32-kbyte 16-bit flash memory arrays to generate 256 kbytes of 32-bit flash memory. these electrically erasable and programmable arrays serve as non-volatile program and data memory. the flash memory is ideal for program and data stor age for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. the cfm interfaces to the cold fire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. a backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath fo r the dma. flash memory may also be programmed via the ezport, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible wi th most spi bus flash memory chips. 1.1.6 power management the mcf5213 incorporates several low-power modes of operation entered under program control and exited by several external trigger events. an integrated power-on reset (por) circuit moni tors the input supply and forces an mcu reset as the supply voltage rises. the low voltage detector (lvd) monitors the suppl y voltage and is configurable to force a reset or interrupt condition if it falls below the lvd trip point. the ram standby switch provides power to ram when the supply voltage to the chip falls below the standby battery voltage.
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 10 1.1.7 flexcan the flexcan module is a communication controller implementing version 2.0 of the can protocol parts a and b. the can protocol can be used as an industrial control serial data bus , meeting the specific requirements of reliable operation in a har sh emi environment with high bandwidth. this instantiation of flexcan has 16 message buffers. 1.1.8 uarts the mcf5213 has three full-duplex uarts that function independently. the three uarts can be clocked by the system bus clock, eliminating the need for an external clock source. on sm aller packages, the third uart is multiplexed with other digital i/o functions. 1.1.9 i 2 c bus the i 2 c bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. this bus is suitable for applicatio ns requiring occasional comm unications over a short distance between many devices. 1.1.10 qspi the queued serial peripheral interface (qsp i) provides a synchronous se rial peripheral interface with queued transfer capabilit y. it allows up to 16 transfers to be queued at once, mi nimizing the need for cpu in tervention between transfers. 1.1.11 fast adc the fast adc consists of an eight-channel input select multip lexer and two independent sample and hold (s/h) circuits feeding separate 12-bit adcs. the two separate converters store their results in accessible buffe rs for further processing. the adc can be configured to perform a single scan and halt, a scan when triggered, or a progr ammed scan sequence repeatedly until manually stopped. the adc can be configured for sequential or simultaneous conversion. when configured fo r sequential conversions, up to eight channels can be sampled and stored in an y order specified by the channel list register. both adcs may be required during a scan, depending on the inputs to be sampled. during a simultaneous conversion, both s/ h circuits are used to capture two diff erent channels at the same time. this configuration requires that a single channel may no t be sampled by both s/h circuits simultaneously. optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limi t registers) or at several diff erent zero crossing conditions. 1.1.12 dma timers (dtim0?dtim3) there are four independent, dma transf er capable 32-bit timers (dtim0, dtim1, dtim2, and dtim3) on the mcf5213. each module incorporates a 32-bit timer with a separate register set for configuration and contro l. the timers can be configure d to operate from the system clock or from an external clock source using one of the dtin n signals. if the system clock is selected, it can be divided by 16 or 1. the input clock is further divide d by a user-programmable 8-bit pr escaler that clocks the actual timer counter register (tcr n ). each of these timers can be configured for input capture or reference (output) compare mode. timer events may optionally cause in terrupt requests or dma transfers.
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 11 1.1.13 general purpose timer (gpt) the general purpose timer (gpt) is a four-channel timer modul e consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. each of the four channels can be configured for input capture or output compare. additionally, channel th ree, can be configured as a pulse accumulator. a timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. the input capture and output compare functions allow simulta neous input waveform measurements and output waveform generation. the input capture function can capture the time of a selected transition edge. th e output compare function can generate output waveforms and timer softwa re delays. the 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.1.14 periodic interrupt timers (pit0 and pit1) the two periodic interrupt timers (pit0 and pit1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. e ach timer can count down from the value written in its pit modulus register or it can be a free-runnin g down-counter. 1.1.15 pulse-width modulation (pwm) timers the mcf5213 has an 8-channel, 8-bit pw m timer. each channel has a programmable period and duty cycle as well as a dedicated counter. each of the modulator s can create independent continuous wavefo rms with software-selectable duty rates from 0% to 100%. the pwm outputs have programmable polari ty, and can be programmed as left aligned outputs or center aligned outputs. for higher period and duty cycle reso lution, each pair of adjacent channels ([7:6], [5:4], [3:2 ], and [1:0]) c an be concatenated to form a single 16-bit cha nnel. the module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels. 1.1.16 software watchdog timer the watchdog timer is a 32-bit timer that facilitates recove ry from runaway code. the watchdog counter is a free-running down-counter that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown. 1.1.17 phase-locked loop (pll) the clock module contains a crystal oscillator, 8 mhz on-chip re laxation oscillator (oco), phase-locked loop (pll), reduced frequency divider (rfd), low-power divide r status/control registers, and control logic. to improve noise immunity, the pll, crystal oscillator, and relaxation oscilla tor have their own power supply inputs: vddpll and vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 1.1.18 interrupt controller (intc) the mcf5213 has a single interrupt controller that supports up to 63 interrupt sources. there are 56 programmable sources, 49 of which are assigned to unique periphera l interrupt requests. the remaining seven s ources are unassigned and may be used for software interrupt requests. 1.1.19 dma controller the direct memory access (dma) controller provides an efficient way to move blocks of data with minimal processor intervention. it has four channels that allow byte, word, longw ord, or 16-byte burst line transf ers. these transfers are trigge red by software explicitly setting a dcr n [start] bit or by the occurrence of certain uart or dma timer events.
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 12 1.1.20 reset the reset controller determines the source of reset, asserts the approp riate reset signals to the system, and keeps track of wh at caused the last reset. there are seven sources of reset: ? external reset input ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock ? pll loss of clock ?software ? low-voltage detector (lvd) control of the lvd and its associated rese t and interrupt are managed by the reset cont roller. other registers provide status f lags indicating the last source of reset and a cont rol bit for software assertion of the rsto pin. 1.1.21 gpio nearly all pins on the mcf5213 have general purpose i/o capabi lity and are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins. 1.1.22 part numbers and packaging this product is rohs-compliant. refer to the product page at freescale.com or contact your sales office for up-to-date rohs information. table 2. orderable part number summary freescale part number description speed package temperature MCF5211cae66 MCF5211 coldfire microcontroller 66 mhz 64 lqfp -40 to +85 c MCF5211cep66 MCF5211 coldfire microcontroller, flexcan 66 mhz 64 qfn -40 to +85 c MCF5211lcep66 MCF5211 coldfire microcontroller 66 mhz 64 qfn -40 to +85 c MCF5211lcvm66 MCF5211 coldfire microcontroller 66 mhz 81 mapbga -40 to +85 c MCF5211lcvm80 MCF5211 coldfire microcontroller 80 mhz 81 mapbga -40 to +85 c mcf5212cae66 mcf5212 coldfire microcontroller 66 mhz 64 lqfp -40 to +85 c mcf5212lcvm66 mcf5212 coldfire microcontroller 66 mhz 81 mapbga -40 to +85 c mcf5212lcvm80 mcf5212 coldfire microcontroller 80 mhz 81 mapbga -40 to +85 c mcf5213caf66 mcf5213 coldfire microcontr oller, flexcan 66 mhz 100 lqfp -40 to +85 c mcf5213caf80 mcf5213 coldfire microcontr oller, flexcan 80 mhz 100 lqfp -40 to +85 c mcf5213lcvm66 mcf5213 coldfire microcontroller, flexcan 66 mhz 81 mapbga -40 to +85 c mcf5213lcvm80 mcf5213 coldfire microcontroller, flexcan 80 mhz 81 mapbga -40 to +85 c
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 13 figure 2 shows the pinout configuration for the 100 lqfp. figure 2. 100 lqfp pin assignments an5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v dd v dd v ss urts1 test ucts0 utxd0 urts0 scl sda qspi_cs3 qspi_cs2 v dd v ss qspi_din qspi_dout qspi_clk qspi_cs1 qspi_cs0 rcon v dd v dd v ss 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v ss v ddpll extal xtal v sspll pst3 pst2 v dd v ss pst1 pst0 pstclk pwm7 gpt3 gpt2 pwm5 gpt1 gpt0 v dd v ss v stby an6 an7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 urxd1 utxd1 ucts1 rsto rsti irq7 irq6 v dd v ss irq5 irq4 irq3 irq2 irq1 allpst ddata3 ddata2 v ss v dd dso dsi ddata1 ddata0 bkpt 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 jtag_en ucts2 urxd2 utxd2 urts2 dtin2 dtin3 pwm3 v dd v ss dtin0 dtin1 pwm1 clkmod1 clkmod0 v dd v ss an0 an1 an2 an3 v ssa v rl v rh v dda v ss urxd0 an4 dsclk
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 14 figure 3 shows the pinout configuration for the 81 mapbga. figure 3. 81 mapbga pin assignments v ss utxd1 rsti irq5 irq3 allpst tdo tms v ss a 123456789 urts1 urxd1 rsto irq6 irq2 trst tdi v dd pll extal b ucts0 test ucts1 irq7 irq4 irq1 tclk v ss pll xtal c urxd0 utxd0 urts0 v ss v dd v ss pwm7 gpt3 gpt2 d scl sda v dd v dd v dd v dd v dd pwm5 gpt1 e qspi_cs3 qspi_cs2 qspi_din v ss v dd v ss gpt0 v stby an4 f qspi_dout qspi_clk rcon dtin1 clkmod0 an2 an3 an5 an6 g qspi_cs0 qspi_cs1 dtin3 dtin0 clkmod1 an1 v ssa v dda an7 h v ss jtag_en dtin2 pwm3 pwm1 an0 v rl v rh v ssa j
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 15 figure 4 shows the pinout configuration for the 64 lqfp and 64 qfn. figure 4. 64 lqfp and 64 qfn pin assignments table 3 shows the pin functions by primary and alternate purpos e, and illustrates which p ackages contain each pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd urts1 test ucts0 urxd0 utxd0 scl sda v dd v ss qspi_din qspi_dout qspi_clk qspi_cs0 rcon 64-pin packages 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v ss urxd1 utxd1 ucts1 rsto rst i irq7 irq4 irq1 allpst dsclk v ss v dd dso dsi bkpt urts0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 jtag_en dtin2 dtin3 v dd v ss dtin0 dtin1 clkmod0 an0 an1 an2 an3 v ssa v rl v rh v dda 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ddpll extal xtal v sspll pstclk gpt3 gpt2 gpt1 gpt0 v dd v ss v stby an4 an5 an6 an7
mcf5213 coldfire microcontroller, rev. 3 freescale semiconductor 16 mcf5213 family configurations table 3. pin functions by primary and alternate purpose pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn adc an7 ? ? gpio low fast ? 51 h9 33 an6 ? ? gpio low fast ? 52 g9 34 an5 ? ? gpio low fast ? 53 g8 35 an4 ? ? gpio low fast ? 54 f9 36 an3 ? ? gpio low fast ? 46 g7 28 an2 ? ? gpio low fast ? 45 g6 27 an1 ? ? gpio low fast ? 44 h6 26 an0 ? ? gpio low fast ? 43 j6 25 synca 3 ? ? ?n/an/a???? syncb 3 ? ? ?n/an/a???? vdda ? ? ? n/a n/a ? 50 h8 32 vssa ? ? ? n/a n/a ? 47 h7, j9 29 vrh ? ? ? n/a n/a ? 49 j8 31 vrl ? ? ? n/a n/a ? 48 j7 30 clock generation extal ? ? ? n/a n/a ? 73 b9 47 xtal ? ? ? n/a n/a ? 72 c9 46 vddpll ? ? ? n/a n/a ? 74 b8 48 vsspll ? ? ? n/a n/a ? 71 c8 45 debug data allpst ? ? ? high fast ? 86 a6 55 ddata[3:0] ? ? gpio high fast ? 84,83,78,77 ? ? pst[3:0] ? ? gpio high fast ? 70,69,66,65 ? ? i 2 c scl cantx 4 utxd2 gpio pdsr[0] psrr[0] pull-up 5 10 e1 8 sda canrx 3 urxd2 gpio pdsr[0] psrr[0] pull-up 5 11 e2 9
mcf5213 family configurations mcf5213 coldfire microcontroller, rev. 3 freescale semiconductor 17 interrupts irq7 ? ? gpio low fast pull-up 95 c4 58 irq6 ? ? gpio low fast pull-up 94 b4 ? irq5 ? ? gpio low fast pull-up 91 a4 ? irq4 ? ? gpio low fast pull-up 90 c5 57 irq3 ? ? gpio low fast pull-up 89 a5 ? irq2 ? ? gpio low fast pull-up 88 b5 ? irq1 synca pwm1 gpio high fast pull-up 5 87 c6 56 jtag/bdm jtag_en ? ? ? n/a n/a pull-down 26 j2 17 tclk/ pstclk clkout ? ? high fast pull-up 6 64 c7 44 tdi/dsi ? ? ? n/a n/a pull-up 6 79 b7 50 tdo/dso? ? ?highfast?80a751 tms /bkpt ? ? ? n/a n/a pull-up 6 76 a8 49 trst /dsclk ? ? ? n/a n/a pull-up 6 85 b6 54 mode selection 7 clkmod0 ? ? ? n/a n/a pull-down 7 40 g5 24 clkmod1 ? ? ? n/a n/a pull-down 7 39 h5 ? rcon / ezpcs ? ? ? n/a n/a pull-up 21 g3 16 pwm pwm7 ? ? gpio pdsr[31] psrr[31] ? 63 d7 ? pwm5 ? ? gpio pdsr[30] psrr[30] ? 60 e8 ? pwm3 ? ? gpio pdsr[29] psrr[29] ? 33 j4 ? pwm1 ? ? gpio pdsr[28] psrr[28] ? 38 j5 ? table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn
mcf5213 coldfire microcontroller, rev. 3 freescale semiconductor 18 mcf5213 family configurations qspi qspi_din/ ezpd canrx 4 urxd1 gpio pdsr[2] psrr[2] ? 16 f3 12 qspi_dout/ ezpq cantx 4 utxd1 gpio pdsr[1] psrr[1] ? 17 g1 13 qspi_clk/ ezpck scl urts1 gpio pdsr[3] psrr[3] pull-up 8 18 g2 14 qspi_cs3 synca syncb gpio pdsr[7] psrr[7] ? 12 f1 ? qspi_cs2 ? ? gpio pdsr[6] psrr[6] ? 13 f2 ? qspi_cs1 ? ? gpio pdsr[5] psrr[5] ? 19 h2 ? qspi_cs0 sda ucts1 gpio pdsr[4] psrr[4] pull-up 8 20 h1 15 reset 9 rsti ? ? ? n/a n/a pull-up 9 96 a3 59 rsto ? ? ?highfast?97b360 test test ? ? ? n/a n/a pull-down 5 c2 3 timers, 16-bit gpt3 ? pwm7 gpio pdsr[23] psrr[23] pull-up 10 62 d8 43 gpt2 ? pwm5 gpio pdsr[22] psrr[22] pull-up 10 61 d9 42 gpt1 ? pwm3 gpio pdsr[21] psrr[21] pull-up 10 59 e9 41 gpt0 ? pwm1 gpio pdsr[20] psrr[20] pull-up 10 58 f7 40 timers, 32-bit dtin3 dtout3 pwm6 gpio pdsr[19] psrr[19] ? 32 h3 19 dtin2 dtout2 pwm4 gpio pdsr[18] psrr[18] ? 31 j3 18 dtin1 dtout1 pwm2 gpio pdsr[17] psrr[17] ? 37 g4 23 dtin0 dtout0 pwm0 gpio pdsr[16] psrr[16] ? 36 h4 22 uart 0 ucts0 canrx ? gpio pdsr[11] psrr[11] ? 6 c1 4 urts0 cantx ? gpio pdsr[10] psrr[10] ? 9 d3 7 urxd0 ? ? gpio pdsr[9] psrr[9] ? 7 d1 5 utxd0 ? ? gpio pdsr[8] psrr[8] ? 8 d2 6 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn
mcf5213 family configurations mcf5213 coldfire microcontroller, rev. 3 freescale semiconductor 19 uart 1 ucts1 synca urxd2 gpio pdsr[15] psrr[15] ? 98 c3 61 urts1 syncb utxd2 gpio pdsr[14] psrr[14] ? 4 b1 2 urxd1 ? ? gpio pdsr[13] psrr[13] ? 100 b2 63 utxd1 ? ? gpio pdsr[12] psrr[12] ? 99 a2 62 uart 2 ucts2 ? ? gpio pdsr[27] psrr[27] ? 27 ? ? urts2 ? ? gpio pdsr[26] psrr[26] ? 30 ? ? urxd2 ? ? gpio pdsr[25] psrr[25] ? 28 ? ? utxd2 ? ? gpio pdsr[24] psrr[24] ? 29 ? ? flexcan canrx 4 ,11 n/an/a???? cantx 4 , 11 n/an/a???? vstby vstby ? ? ? n/a n/a ? 55 f8 37 vdd vdd ? ? ? n/a n/a ? 1,2,14,22, 23,34,41, 57,68,81,93 d5,e3?e7, f5 1,10,20,39,5 2 vss vss ? ? ? n/a n/a ? 3,15,24,25,3 5,42,56, 67,75,82,92 a1,a9,d4,d 6,f4,f6,j1 11,21,38, 53,64 1 the pdsr and pssr registers are described in the general purpose i/o chap ter. all programmable signals default to 2 ma drive and fast slew rate in normal (single-chip) mode. 2 all signals have a pull-up in gpio mode. 3 these signals are multiplexed on other pins. 4 the multiplexed cantx and canrx signals are not available on the MCF5211 or mcf5212. 5 for primary and gpio functions only. 6 only when jtag mode is enabled. 7 clkmod0 and clkmod1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended. 8 for secondary and gpio functions only. 9 rsti has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended. 10 for gpio function. primary function ha s pull-up control within the gpt module. 11 cantx and canrx are secondary functions only. table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 20 1.2 reset signals table 4 describes signals used to reset the chip or as a reset indication. 1.3 pll and clock signals table 5 describes signals used to support the on-chip clock generation circuitry. 1.4 mode selection table 6 describes signals used in mode selection; table 7 describes the particular clocking modes. table 4. reset signals signal name abbreviation function i/o reset in rsti primary reset input to the device. asserting rsti for at least 8 cpu clock cycles immediately resets the cpu and peripherals. i reset out rsto driven low for 1024 cpu clocks after the reset source has deasserted. o table 5. pll and clock signals signal name abbreviation function i/o external clock in extal crystal oscillator or external clock input except when the on-chip relaxation oscillator is used. i crystal xtal crystal oscillator output except when clkmod1=1, then sampled as part of the clock mode selection mechanism. o clock out clkout this output signal reflects the internal system clock. o table 6. mode selection signals signal name abbreviation function i/o clock mode selection clkmod[1:0] selects the clock boot mode. i reset configuration rcon the serial flash programming mode is entered by asserting the rcon pin (with the test pin negated) as the chip comes out of reset. during this mode, the ezport has access to the flash memory which can be programmed from an external device. test test reserved for factory testing only and in normal modes of operation should be connected to vss to prevent unintentional activation of test functions. i table 7. clocking modes clkmod[1:0] xtal configure the clock mode. 00 0 pll disabled, clock driven by external oscillator 00 1 pll disabled, clock driven by on-chip oscillator 01 n/a pll disabled, clock driven by crystal 10 0 pll in normal mode, clock driven by external oscillator 10 1 pll in normal mode, clock driven by on-chip oscillator 11 n/a pll in normal mode, clock driven by crystal
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 21 1.5 external interrupt signals table 8 describes the external interrupt signals. 1.6 queued serial peripheral interface (qspi) table 9 describes the qspi signals. 1.7 i 2 c i/o signals table 10 describes the i 2 c serial interface module signals. table 8. external interrupt signals signal name abbreviation function i/o external interrupts irq [7:1] external interrupt sources. i table 9. queued serial peripheral interface (qspi) signals signal name abbreviation function i/o qspi synchronous serial output qspi_dout provides the serial data from t he qspi and can be programmed to be driven on the rising or falling edge of qspi_clk. o qspi synchronous serial data input qspi_din provides the serial data to the qspi and can be programmed to be sampled on the rising or falling edge of qspi_clk. i qspi serial clock qspi_clk provides the serial cl ock from the qspi. the polarity and phase of qspi_clk are programmable. o synchronous peripheral chip selects qspi_cs[3:0] qspi peripheral chip select; can be programmed to be active high or low. o table 10. i 2 c i/o signals signal name abbreviation function i/o serial clock scl open-drain clock signal for the for the i 2 c interface. when the bus is in master mode, this clock is driven by the i 2 c module; when the bus is in slave mode, this cl ock becomes the clock input. i/o serial data sda open-drain signal that serves as the data input/output for the i 2 c interface. i/o
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 22 1.8 uart module signals table 11 describes the uart module signals. 1.9 dma timer signals table 12 describes the signals of the four dma timer modules. 1.10 adc signals table 13 describes the signals of the analog-to-digital converter. table 11. uart module signals signal name abbreviation function i/o transmit serial data output utxd n transmitter serial data outputs fo r the uart modules. the output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. o receive serial data input urxd n receiver serial data inputs for the uart modules. data is received on this pin lsb first. when the uart clock is stopped for power-down mode, any transition on this pin restarts the clock. i clear-to-send ucts n indication to the uart modules that they can begin data transmission. i request-to-send urts n automatic request-to-send outputs from the uart modules. this signal can also be configured to be asserted and negated as a function of the rxfifo level. o table 12. dma timer signals signal name abbreviation function i/o dma timer input dtin event input to the dma timer modules. i dma timer output dtout programmable output from the dma timer modules. o table 13. adc signals signal name abbreviation function i/o analog inputs an[7:0] inputs to the analog-to-digital converter. i analog reference v rh reference voltage high and low inputs. i v rl i analog supply v dda isolate the adc circuitry from power supply noise. ? v ssa ? adc sync inputs synca / syncb these signals can initiate an analog-to-digital conversion process. i
mcf5213 family configurations mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 23 1.11 general purpose timer signals table 14 describes the general purpose timer signals. 1.12 pulse width modulator signals table 15 describes the pwm signals. 1.13 debug support signals these signals are used as th e interface to the on-chip jtag controller and the bdm logic. table 14. gpt signals signal name abbreviation function i/o general purpose timer input/output gpt[3:0] inputs to or outputs from the general purpose timer module. i/o table 15. pwm signals signal name abbreviation function i/o pwm output channels pwm[7:0] pulse width modulated output for pwm channels. o table 16. debug support signals signal name abbreviation function i/o jtag enable jtag_en select between debug module and jtag signals at reset. i test reset trst this active-low signal is used to initialize the jtag logic asynchronously. i test clock tclk used to synch ronize the jtag logic. i test mode select tms used to sequence the jtag state machine. tms is sampled on the rising edge of tclk. i test data input tdi serial input for test inst ructions and data. tdi is sampled on the rising edge of tclk. i test data output tdo serial output for test inst ructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. o development serial clock dsclk development serial clock - internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising bus clock edges.) clocks the serial communication port to the debug module during packet transfers. maximum frequency is pstclk/5. at the synchroniz ed rising edge of dsclk, the data input on dsi is sampled and dso changes state. i breakpoint bkpt breakpoint - input used to request a manual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is reflected on processor status/debug data signals (pst[3:0] and pstddata[7:0]) as the value 0xf. if csr[bkd] is set (disabling normal bkpt functionality), asserting bkpt generates a debug interrupt exception in the processor. i
mcf5213 coldfire micr ocontroller, rev. 3 mcf5213 family configurations freescale semiconductor 24 1.14 ezport signal descriptions table contains a list of ez port external signals. development serial input dsi development serial input - internally synchronized input that provides data input for the serial communication port to the debug module, after the dsclk has been seen as high (logic 1). i development serial output dso development serial output - prov ides serial output communication for debug module responses. dso is registered internally. the output is delayed from the validation of dsclk high. o debug data ddata[3:0] display captured processor data and breakpoint status. the clkout signal can be used by the development system to know when to sample ddata[3:0]. o processor status clock pstclk processor status clock - delayed version of the processor clock. its rising edge appears in the center of valid pst and ddata output. pstclk indicates when the development system should sample pst and ddata values. if real-time trace is not used, setting csr[pcd] keeps pstclk, and pst and ddata outputs from toggling without disabling triggers. non-quiescent operation can be reenabled by clearing csr[pcd], although the external development systems must resynchronize with the pst and ddata outputs. pstclk starts clocking only when the first non-zero pst value (0xc, 0xd, or 0xf) occurs during system reset exception processing. o processor status outputs pst[3:0] indicate core status. debug mode timing is synchronous with the processor clock; status is unrelate d to the current bus transfer. the clkout signal can be used by the development system to know when to sample pst[3:0]. o all processor status outputs allpst logical and of pst[3:0]. the clkout signal can be used by the development system to know when to sample allpst. o table 17. ezport signal descriptions signal name abbreviation function i/o ezport clock ezpck shift clock for ezport transfers. i ezport chip select ezpcs chip select for signalling the start and end of serial transfers. i ezport serial data in ezpd ezpd is sampled on the rising edge of ezpck. i ezport serial data out ezpq ezpq transitions on the falling edge of ezpck. o table 16. debug support signals (continued) signal name abbreviation function i/o
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 25 1.15 power and ground pins the pins described in table 18 provide system power and ground to the chip. mu ltiple pins are provided for adequate current capability. all power supply pins must have adequate bypass capacitance for high- frequency noise suppression. 2 electrical characteristics this section contains electrical specifi cation tables and reference timing diagrams for the mcf5213 microcontroller unit, including detailed information on power considerations, dc /ac electrical characteristics, and ac timing specifications. note the parameters specified in this data sheet supersede any values found in the module specifications. table 18. power and ground pins signal name abbreviation function pll analog supply vddpll, vsspll dedicated power supply signals to isolate the sensitive pll analog circuitry from the normal levels of noise present on the digital power supply. positive supply vdd these pins supply positive power to the core logic. ground vss this pin is the negative supply (ground) to the chip.
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 26 2.1 maximum ratings table 19. absolute maximum ratings 1, 2 1 functional operating conditions are given in dc el ectrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against dam age due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (v ss or v dd ). rating symbol value unit supply voltage v dd ?0.3 to + 4.0 v clock synthesizer supply voltage v ddpll ?0.3 to + 4.0 v ram standby supply voltage v stby ?0.3 to + 4.0 v digital input voltage 3 3 input must be current limited to the i dd value specified. to determine the value of the required current-limiting resistor, calculat e resistance values for positive and negative clamp voltages, then use the larger of the two values. v in ?0.3 to + 4.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v instantaneous maximum current single pin limit (applies to all pins) 4, 5 4 all functional non-supply pins are internally clamped to v ss and v dd . 5 the power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in the external power supply going out of regulation. ensure that the external v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consuming power (e.g., no clock). i dd 25 ma operating temperature range (packaged) t a (t l - t h ) ?40 to 85 c storage temperature range t stg ?65 to 150 c
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 27 2.2 current consumption table 20. current consumption in low-power mode 1,2 1 all values are measured with a 3.30 v power supply 2 refer to the power management chapter in the mcf5 213 reference manual for more information on low-power modes. mode 8mhz (typ) 3 3 clkout and all peripheral clocks except uart0 a nd cfm off before entering low power mode. clkout is disabled. all code executed from flash memory . code run from sram reduces power consumption further. tests performed at room temperature. 16mhz (typ) 2 64mhz (typ) 2 80mhz (typ) 2 units stop mode 3 (stop 11) 4 4 see the description of the low-power control regist er (lpcr) in the mcf5213 reference manual for more information on stop modes 0?3. 0.13 ma stop mode 2 (stop 10) 4 2.29 stop mode 1 (stop 01) 4 ,5 5 results are identical to stop 00 for typical values because they only differ by clkout power consumption. clkout is already disabled in th is instance prior to entering low power mode. typical current consumption in low-power modes 2.80 3.08 4.76 5.38 stop mode 0 (stop 00) 4 2.80 3.08 4.76 5.39 wait / doze 11.12 20.23 30.17 33.36 run 12.40 22.74 39.92 45.47 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 0 8 16 24 32 40 48 56 64 72 80 system clock (mhz) ma @ 3.3v stop 0 - flash stop 1 - flash stop 2 - flash stop 3 - flash wait/doze - flash run - flash
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 28 2.3 thermal characteristics table 22 lists thermal resistance values. table 21. typical active current consumption specifications characteristic symbol typical 1 active (sram) 1 tested at room temperature with cpu pol ling a status register. all clocks were off except the uart and cfm (when running from flash memory). typical 1 active (flash) peak 2 2 peak current measured with all modules active , and default drive strength with matching load. unit 1 mhz core & i/o i dd ?3.48?ma 8 mhz core & i/o 7.28 13.37 19.02 16 mhz core & i/o 12.08 25.08 35.66 64 mhz core & i/o 40.14 54.62 85.01 80 mhz core & i/o 49.2 64.09 100.03 ram standby supply current ? normal operation: v dd > v stby - 0.3 v ? transient condition: v stby - 0.3 v > v dd > v ss + 0.5 v ? standby operation: v dd < v ss + 0.5 v i stby n/a 3 n/a 3 n/a 3 3 due to the errata ?non-function al ram standby supply? in the mcf5213 device errata , v stby should be connected directly to v dd and cannot be used for ram standby operation. n/a 3 n/a 3 n/a 3 a ma a analog supply current ? normal operation ? low-power stop i dda ? ? ? ? 16 50 ma a table 22. thermal characteristics characteristic symbol value unit 100 lqfp junction to ambient, natural convection single layer board (1s) ja 53 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 39 1,3 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 42 1,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 33 1,3 c / w junction to board ? jb 25 4 c / w junction to case ? jc 9 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature ? t j 105 o c
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 29 81 mapbga junction to ambient, natura l convection single layer board (1s) ja 61 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 35 2,3 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 50 2,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 31 2,3 c / w junction to board ? jb 20 4 c / w junction to case ? jc 12 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature ? t j 105 o c 64 lqfp junction to ambient, natural convection single layer board (1s) ja 62 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 43 1,3 c / w junction to ambient (@200 ft/min) single layer board (1s) jma 50 1,3 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 36 1,3 c / w junction to board ? jb 26 4 c / w junction to case ? jc 9 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature ? t j 105 o c 64 qfn junction to ambient, natural convection single layer board (1s) ja 68 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 24 1,3 c / w junction to ambient (@200 ft/min) single layer board (1s) jma 55 1,3 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 19 1,3 c / w junction to board ? jb 8 4 c / w junction to case (bottom) ? jc 0.6 5 c / w junction to top of package natural convection jt 3 6 c / w maximum operating junction temperature ? t j 105 o c 1 ja and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in th e system design to prevent device junction temperatures from exceeding the rated sp ecification. system designers should be aw are that device junction temperatures can be significantly influenced by board la yout and surrounding devices. conformanc e to the device junction temperature specification can be verified by physical meas urement in the custom er?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 3 per jedec jesd51-6 with the board jesd51-7) horizontal. 4 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). 6 thermal characterization parameter i ndicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not av ailable, the thermal characterization parameter is written in conformance with psi-jt. table 22. thermal characteristics (continued) characteristic symbol value unit
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 30 2.4 flash memory characteristics the flash memory charact eristics are shown in table 23 and table 24 . the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = chip internal power, i dd v dd , watts p i/o = power dissipation on input and output pins ? user determined, watts for most applications p i/o < p int and can be ignored. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular pa rt. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equat ions (1) and (2) iteratively for any value of t a . table 23. sgfm flash program and erase characteristics (v ddf = 2.7 to 3.6 v) parameter symbol min typ max unit system clock (read only) f sys(r) 0? 66.67 or 80 1 1 depending on packaging; see ta bl e 2 . mhz system clock (program/erase) 2 2 refer to the flash memory section for more information f sys(p/e) 0.15 ? 66.67 or 80 1 mhz table 24. sgfm flash module life characteristics (v ddf = 2.7 to 3.6 v) parameter symbol value unit maximum number of guaranteed program/erase cycles 1 before failure 1 a program/erase cycle is defined as switching the bits from 1 0 1. p/e 10,000 2 2 reprogramming of a flash memory array block prior to erase is not required. cycles data retention at average operating temperature of 85 c retention 10 years t j t a p d jma () + = p d kt j 273 c + () =
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 31 2.5 esd protection 2.6 dc electrical specifications table 25. esd protection characteristics 1, 2 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing is performed per applicable device spec ification at room temperature followed by hot temperature, unless specified othe rwise in the device specification. characteristics symbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 c 100 pf mm circuit description r series 0 c 200 pf number of pulses per pin (hbm) ? positive pulses ? negative pulses ? ? 1 1 ? number of pulses per pin (mm) ? positive pulses ? negative pulses ? ? 3 3 ? interval of pulses ? 1 sec table 26. dc electrical specifications 1 characteristic symbol min max unit supply voltage v dd 3.0 3.6 v standby voltage v stby 3.0 3.6 v input high voltage v ih 0.7 v dd 4.0 v input low voltage v il v ss ? 0.3 0.35 v dd v input hysteresis v hys 0.06 v dd ?mv low-voltage detect trip voltage (v dd falling) v lvd 2.15 2.3 v low-voltage detect hysteresis (v dd rising) v lv d h y s 60 120 mv input leakage current v in = v dd or v ss , digital pins i in ?1.0 1.0 a output high voltage (all inpu t/output and all output pins) i oh = ?2.0 ma v oh v dd ? 0.5 ? v output low voltage (all input/ output and all output pins) i ol = 2.0ma v ol ?0.5v
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 32 2.7 clock source electrical specifications output high voltage (high drive) i oh = -5 ma v oh v dd ? 0.5 ? v output low voltage (high drive) i ol = 5 ma v ol ?0.5v output high voltage (low drive) i oh = -2 ma v oh v dd - 0.5 ? v output low voltage (low drive) i ol = 2 ma v ol ?0.5v weak internal pull up device current, tested at v il max. 2 i apu ?10 ?130 a input capacitance 3 ? all input-only pins ? all input/output (three-state) pins c in ? ? 7 7 pf 1 refer to table 27 for additional pll specifications. 2 refer to ta b l e 3 for pins having internal pull-up devices. 3 this parameter is characterized before qualification rather than 100% tested. table 27. pll electrical specifications (v dd and v ddpll = 2.7 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit pll reference frequency range ? crystal reference ? external reference f ref_crystal f ref_ext 2 2 10.0 10.0 mhz system frequency 1 ? external clock mode ? on-chip pll frequency f sys 0 f ref / 32 66.67 or 80 2 66.67 or 80 2 mhz loss of reference frequency 3, 5 f lor 100 1000 khz self clocked mode frequency 4 f scm 15mhz crystal start-up time 5, 6 t cst ?10ms extal input high voltage ? external reference v ihext 2.0 v dd v extal input low voltage ? external reference v ilext v ss 0.8 v pll lock time 4,7 t lpll ?500 s duty cycle of reference 4 t dc 40 60 % f ref table 26. dc electrical specifications (continued) 1 characteristic symbol min max unit
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 33 2.8 general purpose i/o timing gpio can be configured for certain pins of the qspi, ddr control, timer, uart, and interrupt interfaces. when in gpio mode, the timing specification for these pins is given in table 28 and figure 5 . the gpio timing is met under the following load test conditions: ?50pf/50 for high drive ?25pf/25 for low drive frequency un-lock range f ul ?1.5 1.5 % f ref frequency lock range f lck ?0.75 0.75 % f ref clkout period jitter 4, 5, 8 ,9 , measured at f sys max ? peak-to-peak (clock edge to clock edge) ? long term (averaged over 2 ms interval) c jitter ? ? 10 .01 % f sys on-chip oscillator frequency f oco 7.84 8.16 mhz 1 all internal registers retain data at 0 hz. 2 depending on packaging; see ta b l e 2 . 3 loss of reference frequency is the reference frequency detected internally, which transitions the pll into self clocked mode. 4 self clocked mode frequency is the frequency at which t he pll operates when the reference frequency falls below f lor with default mfd/rfd settings. 5 this parameter is characterized before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. 7 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 9 based on slow system clock of 40 mhz measured at f sys max. table 28. gpio timing num characteristic symbol min max unit g1 clkout high to gpio output valid t chpov ?10ns g2 clkout high to gpio output invalid t chpoi 1.5 ? ns g3 gpio input valid to clkout high t pvch 9?ns g4 clkout high to gpio input invalid t chpi 1.5 ? ns table 27. pll electrical specifications (continued) (v dd and v ddpll = 2.7 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 34 figure 5. gpio timing 2.9 reset timing figure 6. rsti and configuration override timing table 29. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 1 all ac timing is shown with respect to 50% v dd levels unless otherwise noted. num characteristic symbol min max unit r1 rsti input valid to clkout high t rvch 9?ns r2 clkout high to rsti input invalid t chri 1.5 ? ns r3 rsti input valid time 2 2 during low power stop, the synchronizers for the rsti input are bypassed and rsti is asserted asynchronously to the system. thus, rsti must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rsto valid t chrov ?10ns g1 clkout gpio outputs g2 g3 g4 gpio inputs 1 r1 r2 clkout rsti rsto r3 r4 r4
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 35 2.10 i 2 c input/output timing specifications table 30 lists specifications for the i 2 c input timing parameters shown in figure 7 . table 31 lists specifications for the i 2 c output timing parameters shown in figure 7 . table 30. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 start condition hold time 2 t cyc ?ns i2 clock low period 8 t cyc ?ns i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 t cyc ?ns i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 t cyc ?ns i9 stop condition setup time 2 t cyc ?ns table 31. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 1 1 output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 3 1 . the i 2 c interface is designed to scale the actual data transiti on time to move it to the middle of the scl low period. the actual position is affected by the pre scale and division values programmed into the ifdr; however, the numbers given in ta b l e 3 1 are minimum values. start condition hold time 6 t cyc ?ns i2 1 clock low period 10 t cyc ?ns i3 2 2 because scl and sda are open-collector-type outputs, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ??s i4 1 data hold time 7 t cyc ?ns i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3ns i6 1 clock high time 10 t cyc ?ns i7 1 data setup time 2 t cyc ?ns i8 1 start condition setup time (for repeated start condition only) 20 t cyc ?ns i9 1 stop condition setup time 10 t cyc ?ns
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 36 figure 7 shows timing for the values in table 30 and table 31 . figure 7. i 2 c input/output timings 2.11 analog-to-digital converter (adc) parameters table 32 lists specifications for th e analog-to-digital converter. table 32. adc parameters 1 name characteristic min typical max unit v refl low reference voltage v ss ?v refh v v refh high reference voltage v refl ?v dda v v dda adc analog supply voltage 3.0 3.3 3.6 v v adin input voltages v refl ?v refh v res resolution 12 ? 12 bits inl integral non-linearity (full input signal range) 2 ? 2.5 3lsb 3 inl integral non-linearity (10% to 90% input signal range) 4 ? 2.5 3lsb dnl differential non-linearity ? ?1 < dnl < + 1< + 1lsb monotonicity guaranteed f adic adc internal clock 0.1 ? 5.0 mhz r ad conversion range v refl ?v refh v t adpu adc power-up time 5 ?613t aic cycles 6 t rec recovery from auto standby ? 0 1 t aic cycles t adc conversion time ? 6 ? t aic cycles t ads sample time ? 1 ? t aic cycles c adi input capacitance ? see figure 8 ?pf x in input impedance ? see figure 8 ?w i adi input injection current 7 , per pin ? ? 3 ma i vrefh v refh current ? 0 ? m v offset offset voltage internal reference ? 8 15 mv e gain gain error (transfer path) .99 1 1.01 ? v offset offset voltage external reference ? 3tbdmv snr signal-to-noise ratio ? 62 to 66 ? db i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 37 2.12 equivalent circuit for adc inputs figure 10-17 shows the adc input circuit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is closed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to (v refh -v refl )/2, while the other charges to the analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, with the result that a single-ended analog input is switched to a differential voltage centered about (v refh -v refl )/2. the switches switch on every cycle of the adc clock (open one-half adc clock, closed one-half adc clock). there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 pr ovides isolation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a fu nction of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the channel select mux; 100 s 4. sampling capacitor at the sample and hold circuit. capacitor c1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pf 5. equivalent input impedance, when the input is selected = figure 8. equivalent circuit for a/d loading thd total harmonic distortion ? ? 75 ? db sfdr spurious free dynamic range ? 67 to 70.3 ? db sinad signal-to-noise plus distortion ? 61 to 63.9 ? db enob effective number of bits 9.1 10.6 ? bits 1 all measurements are preliminary pending full characterization, and made at v dd = 3.3v, v refh = 3.3v, and v refl = ground 2 inl measured from v in = v refl to v in = v refh 3 lsb = least significant bit 4 inl measured from v in = 0.1v refh to v in = 0.9v refh 5 includes power-up of adc and v ref 6 adc clock cycles 7 current that can be injected or sourced from an unselected adc signal input without impacting the performance of the adc table 32. adc parameters 1 (continued) name characteristic min typical max unit 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refh - v refl )/ 2 125w esd resistor 8pf noise damping capacitor 1 (adc clock rate) (1.4 10 -12 )
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 38 2.13 dma timers timing specifications table 33 lists timer module ac timings. 2.14 qspi electrical specifications table 34 lists qspi timings. the values in table 34 correspond to figure 9 . figure 9. qspi timing table 33. timer module ac timing specifications name characteristic 1 1 all timing references to clkout are given to its rising edge. min max unit t1 dtin0 / dtin1 / dtin2 / dtin3 cycle time 3 t cyc ?ns t2 dtin0 / dtin1 / dtin2 / dtin3 pulse width 1 t cyc ?ns table 34. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid ? 10 ns qs3 qspi_clk high to qspi_dout invalid (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 39 2.15 jtag and boundary scan timing figure 10. test clock input timing table 35. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. he nce, it is not associated with any timing. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4 t cyc ?ns j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4?ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data setup time to tclk rise t tapbst 4?ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns tclk v il v ih j3 j3 j4 j4 j2 (input)
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 40 figure 11. boundary scan (jtag) timing figure 12. test access port timing figure 13. trst timing input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst 14 13
electrical characteristics mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 41 2.16 debug ac timing specifications table 36 lists specifications for the debug ac timing parameters shown in figure 15 . figure 14 shows real-time trace ti ming for the values in table 36 . figure 14. real-time trace ac timing table 36. debug ac timing specification num characteristic 66/80 mhz units min max d1 pst, ddata to clkout setup 4 ? ns d2 clkout to pst, ddata hold 1.5 ? ns d3 dsi-to-dsclk setup 1 t cyc ?ns d4 1 1 dsclk and dsi are synchronized internally. d4 is meas ured from the synchronized dsclk input relative to the rising edge of clkout. dsclk-to-dso hold 4 t cyc ?ns d5 dsclk cycle time 5 t cyc ?ns d6 bkpt input data setup time to clkout rise 4 ? ns d7 bkpt input data hold time to clkout rise 1.5 ? ns d8 clkout high to bkpt high z 0.0 10.0 ns clkout pst[3:0] d2 d1 ddata[3:0]
mcf5213 coldfire micr ocontroller, rev. 3 electrical characteristics freescale semiconductor 42 figure 15 shows bdm serial port ac timing for the values in table 36 . figure 15. bdm serial port ac timing dsi dso current next clkout past current dsclk d3 d4 d5
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 43 3 mechanical outline drawings this section describes the physical proper ties of the mcf5213 and its derivatives. 3.1 64-pin lqfp package
mcf5213 coldfire micr ocontroller, rev. 3 mechanical outline drawings freescale semiconductor 44
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 45
mcf5213 coldfire micr ocontroller, rev. 3 mechanical outline drawings freescale semiconductor 46 3.2 64 qfn package
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 47
mcf5213 coldfire micr ocontroller, rev. 3 mechanical outline drawings freescale semiconductor 48
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 49
mcf5213 coldfire micr ocontroller, rev. 3 mechanical outline drawings freescale semiconductor 50 3.3 81 mapbga package
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 51
mcf5213 coldfire micr ocontroller, rev. 3 mechanical outline drawings freescale semiconductor 52 3.4 100-pin lqfp package
mechanical outline drawings mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 53
mcf5213 coldfire micr ocontroller, rev. 3 revision history freescale semiconductor 54 4 revision history table 37. revision history revision description 2 ? formatting, layout, spelling, and grammar corrections. ? added revision history. ? corrected signal names in block diagram to match those in signal description table. ? added the following footnote to the MCF5211 flexcan entry: ?flexcan is available on the MCF5211 only in the 64 qfn package.? ? added an entry for standby voltage (v stby ) to the ?dc electrical specifications? table. ? deleted the pstclk cycle ti me row in the ?debug ac timing specifications? table. ? changed the frequency above the ?min? and ?max? column headings in the ?debug ac timing specifications? table (was 166 mhz, is 66/80 mhz). ? changed the minimum value for snr, thd, sfdr , and sinad in the ?adc parameters? table (was tbd, is ???). ? in the ?pin functions by primary and alternate purpose? table, changed the value in the ?pull-up/pull-down? column for irq2 -irq6 (was ???, is ?pull-up?). ? added values for i oh and i ol to the ?dc electrical specifications? table. ? added load test condition information to the ?general purpose i/o timing? section. ? deleted the ?80 mhz (peak)? column from the ?current consumption in low-power mode? table. ? in the ?typical active current consumption spec ifications? table, changed the typical active (sram) and peak i dd values for the 1 mhz core & i/o entry (were tbd, are ???). ? changed the i stby values in the ?typical active current co nsumption specifications? table (were 0 or tbd, are ???) and added an explanatory footnote referring to the mcf5213 device errata . ? changed the i dda values in the ?typical active current co nsumption specifications? table (were tbd, are 16 ma for normal operation and 50 a for low-power stop). 3 ? formatting, layout, spelling, and grammar corrections. ? synchronized the ?pin functions by primary and alternate purpose? table in this document and the reference manual. ? restructured the part number summary table to include full orderable parts, and changed its name (was ?part number summary?, is ?orderable part number summary?). ? updated the family configurations table to show that flexcan is not available on the mcf5212. ? added specifications for v lv d and v lv d h y s to the ?dc electrical specifications? table.
revision history mcf5213 coldfire micr ocontroller, rev. 3 freescale semiconductor 55
document number: mcf5213ec rev. 3 05/2007 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved.

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